1. Field of the Invention
The present invention is related to a trench semiconductor device and a method of making the same, and particularly, to a trench semiconductor device having a trench metal oxide semiconductor (MOS) transistor device and a trench ESD protection device and a method of making the same.
2. Description of the Prior Art
Power MOS transistor device has high voltage and high current, and it is prone to be damaged by ESD pulse. In order to have a lower threshold voltage, the thickness of the gate oxide layer of the power MOS transistor device made by the integrated circuit process has to be reduced. Under this circumstance, power MOS is prone to be damaged by ESD pulse generated due to friction or other uncertain factors. Therefore, the present power MOS transistor device is usually constructed together with an ESD protection circuit to protect power MOS transistor device from damage. The conventional technology of forming power MOS transistor device fabricates the power MOS transistor device and then makes the ESD protection circuit which requires extra manufacturing process and cost.
U.S. Pat. No. 7,205,196 discloses a method of forming a power MOS transistor device and an ESD protection device. According to its disclosure, the formation of the ESD protection is integrated into the process of forming the power MOS transistor. However, an extra mask is required to define the pattern of the polysilicon layer which increases complexity of the process and the cost.